Custom 8-Bit CPU Architecture, Emulator & Assembler
01Python, C & Logisim Evolution
Designed an 8-bit CPU in Logisim Evolution. Features a custom 32-bit ISA, a functional Emulator written in C, and RGB display capabilities. Modelled CPU logic gates, registers, and memory management to demonstrate a deep understanding of the fetch-decode-execute cycle and low-level hardware-software interfacing. Developed a lightweight Python assembler to translate human-readable assembly into binary format, establishing the project's software toolchain.
ISA Width
32-bit
Architecture
8-bit
Toolchain
3-layer